Semester:
5th
Course Type:
Track Compulsory courses (EYM)
Track:
CΕT (Computer Engineering and Telecoms)
Code:
Κ30
ECTS:
6
TEACHING HOURS per week
Theory:
3
Seminar:
1
Laboratory:
1
Specializations
Foundations of Computer Science (S1):
-
Data and Knowledge Management (S2):
-
Software (S3):
B Βασικό
Hardware and Architecture (S4):
Υ Υποχρεωτικό
Communications and Networking (S5):
-
Signal and Information Processing (S6):
-
Related Courses
Detailed Description
Course Content
ISA of RISC architectures (review)
Basics of pipelining,
Pipelining in MIPS microprocessors.
Datapath and control unit design for pipelined CPU.
Data, control and structural hazards.
Superscalar and out-of-order basics.
Branch prediction.
Cache memories concept.
Caches architectures and algorithms.
Virtual memory.
Input/output devices.
Storage devices performance and reliability.
Microprocessor systems interfacing.
LITERATURE AND STUDY MATERIALS - READING LIST
“Computer Organization and Design: the Hardware/Software Interface”, 4th Edition, D.A.Patterson, J.L.Hennessy, Elsevier/Morgan Kaufmann, 2010.
e-Class link